US Patent 8220068 - Nanowire scanning probe array

http://www.freepatentsonline.com/8220068.html

Scanning probe microscopes are used to analyze semiconductor features on a nanoscale. In order to analyze 3D surfaces and trenches carbon nanotubes have been used as the tips of the scanning probes but it is difficult to mass produce nanotube tipped probes. This patent from IBM teaches a micromachining method for producing nanowire tipped probes so as to facilitate mass production. Claim 1 reads:

1. A structure comprising an array of scanning probes located on a semiconductor wafer, each scanning probe of said array is orientated in a same direction on said semiconductor wafer and comprises:

a cantilever having a bottommost surface on an upper surface of said semiconductor wafer;

a micromachined single-crystal pyramid formed on said cantilever; and

a single-crystal nanowire extending from a top portion of said pyramid, wherein said nanowire is epitaxial with respect to said single-crystal pyramid.                             

US Patent 8187955 - Graphene growth on a carbon-containing semiconductor layer

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This patent from IBM teaches growing graphene films on 200mm or 300mm silicon wafers using a double annealing process. Claim 1 reads:

1. A method of forming a graphene layer including at least one graphene monolayer, said method comprising:

forming a semiconductor-carbon alloy layer comprising a material other than crystalline silicon carbide on a semiconductor substrate;

converting said semiconductor-carbon alloy layer into a semiconductor carbide layer by a first anneal; and

converting an exposed top portion of said semiconductor carbide layer into a graphene layer including at least one graphene monolayer by a second anneal.

US Patent 8129247 - Omega shaped nanowire FET

http://www.freepatentsonline.com/8129247.html

This patent from IBM teaches a method to improve the doping characteristics of nanowires used as the channels of field effect transistors by using epitaxial growth rather than ion implantation. Claim 1 reads:

1. A method for forming a nanowire field effect transistor (FET) device, the method comprising:

forming a nanowire on a semiconductor substrate;

forming a first gate structure on a first portion of the nanowire;

forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure;

removing exposed portions of the nanowire left unprotected by the first spacer; and

epitaxially growing a doped semiconductor material from exposed cross sections of the nanowire to form a first source region and a first drain region.

US Patent 8106383 - Self-aligned graphene transistor

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This patent from IBM teaches a way to achieve material processing of both carbon and oxide to achieve self-aligned fabrication of graphene transistors. Claim 1 reads:

1. A graphene field effect transistor comprising:

a gate stack, the gate stack including a seed layer, a gate oxide formed over the seed layer, and a gate metal formed over the gate oxide;

an insulating layer; and

a graphene sheet displaced between the seed layer and the insulating layer, further comprising:

a spacer formed on a top and both sides of the gate stack.

US Patent 8101474 - Buried-channel graphene field effect device

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It has been found that the gate dielectric can deteriorate the channel mobility of graphene transistors. This patent from IBM teaches a way to manufacture a graphene transistor to avoid this problem. Claim 10 reads:

10. A buried channel graphene device comprising:

a substrate;

a layer of graphene on said substrate;

a layer of amorphous silicon on said graphene layer;

a gate dielectric layer on said amorphous silicon layer;

source and drain contact regions in contact with said graphene layers; and

a gate electrode on said gate dielectric layer in between said source and drain contact regions.

US Patent 8053782 - Graphene phototransistor

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Graphene has become increasing popular in the last few years for its potential in achieving high speed nanoelectronics. This patent from IBM teaches additional advantages of graphene to achieve photodetection over a broader range of wavelengths than conventional semiconductor materials. Claim 1 reads:

1. A photodetecting device comprising:

a. a substrate;

b. a gate oxide layer deposited on said substrate;

c. a channel layer of graphene deposited on said gate oxide layer; and

d. source and drain contact regions disposed on said graphene layer wherein multiple source and drain regions are provided.

US Patent 8026560 - Molecular mass detector using nanowire transistor

http://www.freepatentsonline.com/8026560.html


This patent from IBM teaches a variation of the structure for a field effect transistor in which a resonating nanowire is used as the transistor channel and is used to measure the mass of molecular structures. Claim 1 reads:

1. A molecular detection device comprising:

a source;

a drain;

a nanowire comprising a semiconductor material having a first end clamped to the source and a second end clamped to the drain, wherein at least a portion of a surface of the nanowire is charge-sensitized by the introduction of compounds to the surface; and

a gate, at least a portion of which is separated from one or more of the source and the drain by a dielectric substrate.

US Patent 8013324 - Structurally stabilized semiconductor nanowire

http://www.freepatentsonline.com/8013324.html

There have already been numerous patented designs for sublithographic field effect transistors based on nanowire channels having a surrounding gate structure. This patent from IBM proposes such a nanoFET design with improved structural stability. Claim 1 reads:

1. A semiconductor structure comprising:

a semiconductor nanowire having a constant-width portion located between a first end portion and a second end portion, wherein said constant-width portion has a constant first initial width between said first end portion and said second end portion;

a first semiconductor pad located on a substrate and adjoining said first end portion of said semiconductor nanowire, wherein said first end portion has a second initial width that is greater than said first initial width at an interface with said first semiconductor pad;

a second semiconductor pad located on said substrate and adjoining said second end portion of said semiconductor nanowire, wherein said second end portion has a first width that is greater than said second initial width at an interface with said second semiconductor pad;

a channel region located in said constant-width portion of said semiconductor nanowire and having a doping of a first conductivity type;

a gate dielectric located on and surrounding said channel region; and

a gate electrode located on and surrounding said gate dielectric.

US Patent 7952088 - Multigate graphene transistor

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Modern transistor design are turning toward multigate structures to overcome current leakage and other effects of nanoscale miniaturization. This patent from IBM includes some basic claims for multigate transistor designs in which graphene is used for the channel material. Claim 1 reads:

1. A semiconductor device comprising:

a substrate having a dielectric layer;

at least one graphene layer overlying the dielectric layer;

a back gate structure underlying the at least one graphene layer; and

a semiconductor-containing layer present on the at least one graphene layer, the semiconductor-containing layer including a source region and a drain region separated by an upper gate structure, wherein the upper gate structure is positioned overlying the back gate structure.

US Patent 7951424 - Selective placement of CNTs on oxide surface

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In order to mass produce MOSFETs with carbon nanotube material a relaiable method is necessary to pattern the nanotubes. This patent from IBM teaches techniques compatible with microcontact printing. Claim 1 reads:

1. A method of selective placement of carbon nanotubes on a predetermined surface comprising:

selectively placing without utilizing silylation chemistry a self-assembled monolayer on an upper metal oxide surface of a substrate;

depositing carbon nanotubes from a dispersion on said self-assembled monolayer or on a surface of said substrate not containing said self-assembled monolayer; and

removing excess carbon nanotubes from said substrate.

US Patent 7940381 - Semiconductor nanowire EM sensor

http://www.freepatentsonline.com/7940381.html

This patent from IBM teaches using semiconductor nanowires to detect electromagnetic radiation such as gamma rays, X-rays, ultraviolet radiation, radiation in visible spectrum, or infrared radiation and in which a dye is used to determine the peak absorption wavelength. Claim 1 reads:

1. A semiconductor device comprising:

a semiconductor nanowire located on a substrate and comprising a semiconductor material; and

a dye layer including a chemical coating layer and a metallic element containing layer, wherein said dye layer absorbs electromagnetic radiation, and wherein energy from said absorbed electromagnetic radiation induces electronic excitation in said dye layer and alters free charge carrier density in said semiconductor nanowire,

wherein said chemical coating layer is located on said semiconductor nanowire and comprises a functional material that selectively attaches to said semiconductor material and react with said metallic element containing layer to form a dye material.

US Patent 7932549 - CNT trench capacitors

http://www.freepatentsonline.com/7932549.html

DRAM is a form of volatile semiconductor memory able to achieve high density due to a simple structure of one transistor and one capacitor and is commonly used as a main memory in personal computers. This patent from IBM teaches a way to use carbon nanotubes to fabricate the capacitors of DRAM memory cells. Claim 1 reads:

1. A trench-type storage device comprising:

a substrate;

a trench in said substrate;

multiple conductive carbon nanotubes lining said trench; and

a trench conductor, surrounded by and in direct contact with said multiple conductive carbon nanotubes, filling said trench, wherein said trench conductor and said substrate have a co-planar top surface.

US Patent 7922796 - Chemically modified CNT filters

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This patent from IBM teaches a molecular filter intended for use in 21st century semiconductor clean rooms which use carbon nanotube mats. Claim 1 reads:

1. A filter, comprising:

a filter housing having an inlet and a separate outlet;

a layer of porous walled and closed containers in said filter housing; and

each porous walled and closed container of said layer holding a tangled collection of individual chemically active carbon nanotubes stuck together in a mat, said chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising organic chemically reactive groups on sidewalls of said carbon nanotubes.

US Patent 7902541 - Strained nanowire FET

http://www.freepatentsonline.com/7902541.html

Strained silicon is used in transistor design to improve mobility and switching speed. This patent from IBM includes some basic claims to strained nanowires used in transistor channels. Claim 1 reads:

1. A semiconductor structure comprising:

a semiconductor nanowire adjoined to a first semiconductor pad and a second semiconductor pad, wherein a middle portion of said semiconductor nanowire is longitudinally strained;

a gate dielectric surrounding said longitudinally strained middle portion of said semiconductor nanowire;

a dielectric material layer embedding said first and second semiconductor pads, wherein said dielectric material layer is substantially stress-free;

at least one source-side contact via embedded in said dielectric material layer and contacting said first semiconductor pad; and

at least one drain-side contact via embedded in said dielectric material layer and contacting said second semiconductor pad.

US Patent 7902540 - Fast p-i-n nanowire photodetector

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This patent from IBM teaches nanowire photodetectors as a replacement for lateral trench detectors which can simplify manufacturing. Claim 1 reads:

1. A p-i-n photodetector comprising:

an array of semiconductor nanowires having a first conductivity type dopant present within an entirety of each of the semiconductor nanowires, the array of semiconductor nanowires disposed vertically on a surface of an underlying semiconductor substrate of said first conductivity type;

an intrinsic semiconductor material located on said surface of said semiconductor substrate and directly on a top surface and sidewall surfaces of each semiconductor nanowire of said array; and

a semiconductor material of a second conductivity type located directly on a surface of said intrinsic semiconductor material, wherein said second conductivity type is different from said first conductivity type, and said array of semiconductor nanowires having the first conductivity type and the semiconductor material of the second conductivity type provide p-type and n-type elements of the p-i-n photodetector and the intrinsic semiconductor material separates the p-type and n-type elements of the p-i-n photodetector, and wherein a portion of said semiconductor material of said second conductivity is spaced apart from the surface of the underlying semiconductor substrate by a portion of said intrinsic semiconductor material that is located on said surface of said underlying semiconductor substrate.

US Patent 7897960 - Self-aligned nanotube FET

http://www.freepatentsonline.com/7897960.html

This patent from IBM has relatively early priority (2002) and teaches a variation of vertical nanotube transistors. Claim 1 reads:

1. A carbon-nanotube field effect transistor semiconductor device comprising:

a vertical carbon-nanotube wrapped in a dielectric material exposing first and second ends of the vertical carbon-nanotube;

a source formed at the first end of the vertical carbon-nanotube;

a drain formed at the second end of the vertical carbon-nanotube; and

a plurality of gate metal pillars formed adjacent to a stack comprising the source, the drain, the vertical carbon-nanotube, wherein the drain is at least partially disposed between the plurality of gate metal pillars.

US Patent 7893492 - Nanowire mesh FET

http://www.freepatentsonline.com/7893492.html

MOSFET electronic designs are moving toward multi-gate and surrounding-gate designs to overcome short channel effects of planar transistors. This patent from IBM proposes a nanowire channel surrounding gate design with improved current carrying capability. Claim 1 reads:

1. A semiconductor structure comprising:

a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of a substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;

a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region; and

a spacer located between each vertically stacked and vertically spaced apart semiconductor nanowire and between the gate region and the source region and drain region.

US Patent 7888753 - Nanowire FET sensor

http://www.freepatentsonline.com/7888753.html

This patent from IBM (priority 7/31/2006) includes some broad claims to nanowire transistors used as molecular detection devices. Claim 1 reads:

1. A detection device comprising:

a source;

a drain;

a nanowire comprising a semiconductor material having a first end clamped to the source and a second end clamped to the drain and suspended freely therebetween; and

a gate separated from the nanowire by a distance of up to about ten nanometers.

US Patent 7872334 - CNT diodes

http://www.freepatentsonline.com/7872334.html

In order to transform CNT electronics into commercial devices a necessary requirement will be mechanisms for electrostatic discharge protection compatible with the carbon nanotubes. This patent from IBM teaches one such mechanism based on using both p-type and n-type nanotubes forming diode junctions. Claim 1 reads:

1. A diode, comprising:

said diode comprising an anode and a cathode, said anode comprising a p-type single wall carbon nanotube and said cathode comprising an n-type single wall carbon nanotube, said p-type single wall carbon nanotube in direct and constant physical and electrical contact with said n-type single wall carbon nanotube to form a permanent PN junction;

a first metal pad in physical and electrical contact with said p-type single wall carbon nanotube and a second metal pad in physical and electrical contact with said n-type single wall carbon nanotube; and

wherein said p-type single wall carbon nano-tube has an electron-withdrawing charge transfer complex coating.

US Patent 7838943 - Shared gate for hybrid nanoelectronics

http://www.freepatentsonline.com/7838943.html

CMOS device electronics requires the manufacture of both n-doped and p-doped transistors. However, it can be difficult to achieve both doping types using only carbon nanotubes and hybrid techniques using both conventional MOSFETs with nanotube MOSFETs may be preferable. This patent from IBM teaches such a configuration. Claim 1 reads:

1. A hybrid semiconductor structure comprising:

a semiconductor device comprising a semiconductor substrate having a source region and a drain region separated by a channel region, a first gate dielectric that is present on the channel region and a gate conductor that is present on the first gate dielectric; and

a carbon nanotube transistor comprising a second gate dielectric that is in direct contact with an upper surface of the gate conductor, and a carbon nanotube in direct contact with a portion of the second gate dielectric that is in direct contact with the upper surface of the gate conductor,

wherein said gate conductor is shared for both the semiconductor device and the carbon nanotube transistor.