US Patent 8013324 - Structurally stabilized semiconductor nanowire
http://www.freepatentsonline.com/8013324.html
There have already been numerous patented designs for sublithographic field effect transistors based on nanowire channels having a surrounding gate structure. This patent from IBM proposes such a nanoFET design with improved structural stability. Claim 1 reads:
1. A semiconductor structure comprising:
a semiconductor nanowire having a constant-width portion located between a first end portion and a second end portion, wherein said constant-width portion has a constant first initial width between said first end portion and said second end portion;
a first semiconductor pad located on a substrate and adjoining said first end portion of said semiconductor nanowire, wherein said first end portion has a second initial width that is greater than said first initial width at an interface with said first semiconductor pad;
a second semiconductor pad located on said substrate and adjoining said second end portion of said semiconductor nanowire, wherein said second end portion has a first width that is greater than said second initial width at an interface with said second semiconductor pad;
a channel region located in said constant-width portion of said semiconductor nanowire and having a doping of a first conductivity type;
a gate dielectric located on and surrounding said channel region; and
a gate electrode located on and surrounding said gate dielectric.
There have already been numerous patented designs for sublithographic field effect transistors based on nanowire channels having a surrounding gate structure. This patent from IBM proposes such a nanoFET design with improved structural stability. Claim 1 reads:
1. A semiconductor structure comprising:
a semiconductor nanowire having a constant-width portion located between a first end portion and a second end portion, wherein said constant-width portion has a constant first initial width between said first end portion and said second end portion;
a first semiconductor pad located on a substrate and adjoining said first end portion of said semiconductor nanowire, wherein said first end portion has a second initial width that is greater than said first initial width at an interface with said first semiconductor pad;
a second semiconductor pad located on said substrate and adjoining said second end portion of said semiconductor nanowire, wherein said second end portion has a first width that is greater than said second initial width at an interface with said second semiconductor pad;
a channel region located in said constant-width portion of said semiconductor nanowire and having a doping of a first conductivity type;
a gate dielectric located on and surrounding said channel region; and
a gate electrode located on and surrounding said gate dielectric.
Labels: IBM
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