US Patent 8063448 - Mem-resistor multi-gate FET

http://www.freepatentsonline.com/8063448.html

In order to continue the scaling predicted by Moore's Law multi-gate transistors will be necessary in the coming decade. There has also been an increasing interest in nanoscale thin films to achieve memory resistive effects for non-volatile memory. This patent from Infineon Technologies encompasses both these trends resulting in a multi-gate memory transistor having improved data retention and reduced size. Claim 1 reads:

1. A memory device comprising:

a multi gate field effect transistor having a fin with a contact area comprising a cross section of the fin; and

a programmable memory element abutting the contact area.

US Patent 7847325 - Discrete trap memory mediated by fullerenes

http://www.freepatentsonline.com/7847325.html

There have been a variety of proposals over the past several years for using nanocrystals in the trap oxide of floating gate memory cells to enhance the scalability and reliability of Flash memory. This patent from Infineon Technology teaches a variation of this concept which instead uses fullerenes such as C60 to control the density and distribution of charge traps. Claim 1 reads:

1. A method for manufacturing a memory device, comprising:

arranging a plurality of Fullerenes on an oxide layer to form a mask, wherein the oxide layer is exposed through the mask at gaps between the plurality of Fullerenes;

depositing nano-crystals over the mask; and

trapping the nano-crystals in gaps between the plurality of Fullerenes.

US Patent 7786464 - Nanocrystal enhanced phase change RAM

http://ip.com/patent/US7786464

This patent from Infineon is based on the finding that nanocrystals can be used to increase the current density and thus reduce power requirements for phase change memory. Claim 1 reads:

1. An integrated circuit comprising:

a first electrode;

resistivity changing material coupled to the first electrode;

a second electrode; and

a dielectric material layer between the resistivity changing material and the second electrode, the dielectric material layer comprising nanocrystals.

US Patent 7626190 - Mem-resistor memory with nanowire transistor

http://www.freepatentsonline.com/7626190.html

This patent from Infineon Technologies teaches another variation of memory resistor electronics which uses nanowire transistors with resistive switching material. Claim 1 reads:

1. A memory device, comprising:

a transistor comprising at least one nanowire or nanotube or nanofibre and a transistor gate region, the nanowire or nanotube or nanofibre being self-aligned with respect to the transistor gate region;

wherein the memory device is a resistively switching memory device; and

wherein the nanowire or nanotube or nanofibre directly contacts a switching active material of the resistively switching memory device.

US Patent 7602614 - Nanoparticle interconnect lines within electronic module

http://www.freepatentsonline.com/7602614.html

This patent from Infineon teaches a way to form wiring connections within the body of a plastic circuit board carrier using nanoparticles. Claim 1 reads:

1. An electronic module comprising:

a first and a second component with connections on connection sides of the components;

a wiring block made of plastic with contact pads on its outer sides and with lines comprising nanoparticles with carbonized short-circuit paths between the nanoparticles in its volume, the lines electrically connecting the contact pads on the outer sides to one another according to a circuit layout, the first component and the second component being arranged on different non-opposite outer sides of the wiring block and the connections being connected to the contact pads.

US Patent 7576410 - Nanotube power transistor

http://www.freepatentsonline.com/7576410.html

This patent from Infineon Technologies teaches the formation of a power transistor including nanotubes in the channel allowing for voltages of up to 600V with less complex gate construction. Claim 1 reads:

1. A power transistor, comprising:

a source region;

a drain region;

a semiconductor body arranged between the source region and the drain region;

a plurality of nanotubes connected in parallel and disposed in the semiconductor body, the plurality of nanotubes being electrically insulated from the semiconductor body and electrically connecting the source and drain regions; and

at least one diode formed in the semiconductor body, a portion of the at least one diode being configured to act as a gate electrode for the transistor.

US Patent 7511294 - Nanoparticle RRAM

http://www.freepatentsonline.com/7511294.html

By using voltage pulses to alter the resistance states of certain materials a new form of non-volatile memory called RRAM has been under development over the past year and has recently been popularized by the memristor theory. This patent from Infineon teaches incorporating nanoparticles in the material to reduce the time necessary for data erasure. Claim 1 reads:

1. A resistive memory element for reversibly switching between a high-resistance OFF state and a low-resistance ON state, the resistive memory element comprising:

a reactive electrode;

an inert electrode;

a solid electrolyte arranged between the reactive and inert electrodes; and

a nanoparticle structure arranged on the inert electrode, wherein the nanoparticle structure is formed of a plurality of nanoparticles that are arranged at a distance and are separated from each other so as to define openings within the nanoparticle structure between the nanoparticles through which the solid electrolyte makes contact with the inert electrode, and the openings within the nanoparticle structure have a defined average size.

US Patent 7420199 - Vertical nanowire mem-resistor memory cell

http://www.freepatentsonline.com/7420199.html

Earlier this year HP researchers announced the memristor as a possible candidate for future non-volatile memory designs. Memristors possess a variable resistance switching property which offer potential to replace transistors as Moore's Law becomes more difficult to fulfill. This patent from Infineon Technologies discloses a variation of memristance-type memory using a vertically oriented nanowire as a control electrode for the memristance material. Claim 1 reads:

1. An integrated circuit having a memory cell comprising:

a first electrode comprising a nanowire;

a second electrode; and

resistivity changing material between the first electrode and the second electrode, wherein a portion of the nanowire is laterally surrounded by the resistivity changing material.

US Patent 7339186 - IC chip with dummy nanowires

http://www.freepatentsonline.com/7339186.html

This patent from Infineon teaches a memory device that uses nanowires in an interesting way. The doping of the nanowires is changed to make nonfunctional areas of the memory which makes the content of the memory more difficult to determine by covert observation. Presumably applications are for storing classified or highly secure data. Claim 1 reads:

1. An IC chip comprising an electronic circuit formed with a plurality of nanowires as vertical conductors, vertical diodes or vertical transistors, arranged in a dielectric layer wherein at least one of said nanowires is provided as a dummy, wherein the dummy is unsuitable as a vertical conductor, vertical diode or vertical transistor: wherein at least one dummy is formed by a relevant nanowire being interrupted by a dielectric region formed in the nanowire between first and second doped region; and the nanowires are silicon and the dielectric region is silicon dioxide or silicon nitride.

US PAtent 7321097 - Vertical nanotube electronic component

http://www.freepatentsonline.com/7321097.html

Infineon already holds several of the basic patents to nanowire FETs (see for example US 6,740,910). This patent expands their hold on nanowire electronics by claiming a basic vertical nanotube electronic device. Claim 1 reads:

1. An electronic component, comprising: a first conductive layer; a nonconductive layer on the first conductive layer, the nonconductive layer having a hole through the nonconductive layer; a second conductive layer on the nonconductive layer; and an electrical connection conductively connecting the first conductive layer and the second conductive layer, which are electrically insulated from one another by the nonconductive layer, wherein the electrical connection is formed by at least one nanotube in the hole, the nanotube being a grown nanotube.

US Patent 7319235 - Nanoporous dielectric for resistance switching memory

http://www.freepatentsonline.com/7319235.html

Chalcogenide and conductive polymer materials are attracting increased interest for non-volatile memory. This patent from Infineon teaches nanoporous materials as an alternative material that can achieve a better stability under temperature change. Claim 1 reads:

1. A nonvolatile, resistively switching memory cell, comprising: a layer of a solid-state ion conductor arranged between a first electrode and a second electrode, wherein the solid-state ion conductor includes a nanoporous low-k dielectric and is free of chalcogenide glass, wherein the porosity of the dielectric is in the range of 1 to 50%, and wherein the dielectric includes ions of a metal from which one of the electrodes is formed.

US Patent 7301779 - CNT chip interconnects

http://www.freepatentsonline.com/7301779.html

In order to connect multiple electronic circuit chips together a variety of methods are known using solder and wire bond connections. This patent from Infineon teaches using carbon nanotubes as electrical interconnect elements to provide better mechanical flexibility and current carrying ability than prior interconnect materials. Claim 1 reads:

1. An electronic chip assembly comprising: a first electronic chip; a second electronic chip; the first electronic chip having a plurality of external chip contacts to which a multiplicity of nanotubes are applied in order to make contact between the first electronic chip and the second electronic chip; the second electronic chip having a plurality of external chip contacts that are free of nanotubes and that can be brought into contact with the nanotubes that have been applied to the external chip contacts of the first electronic chip; and wherein the nanotubes of one external chip contact of the first electronic chip are brought into contact with one external chip contact of the second electronic chip.

US Patent 7268423 - Carbon nanotubes for rewiring plate

http://www.freepatentsonline.com/7268423.html

When connecting a semiconductor chip to a circuit board differing thermal expansion effects can cause mechanical problems. In order to overcome this difficulty a rewiring plate is often used as a buffer. This patent from Infineon teaches the incorporation of carbon nanotubes in such rewiring plates to increase connection density. Claim 1 reads:

1. A rewiring plate for components with a dense connection grid, the rewiring plate comprising: a base body having passages and including silicone; and a plurality of carbon nanotubes positioned within the passages, a lower end of the passages opening out into contact connection surfaces, wherein the carbon nanotubes form an electrically conductive connection from the contact connection surfaces to a front surface of the base body.

US Patent 7265376 - Vertical nanochannel non-volatile memory

http://www.freepatentsonline.com/7265376.html

Vertical nanochannel FETs are likely to be the next (last?) stage of electronic design that exploits Moore's law, which predicts an exponential increase in circuit density over time. This patent from Infineon Technologies is fairly fundamental to the use of vertical nanochannel FETs in electrically programmable memory. Claim 1 reads:

1. A nonvolatile memory cell comprising: a vertical field-effect transistor with a nanoelement designed as the channel region, the nanoelement containing at least one of a nanotube, a bundle of nanotubes, or a nanorod; and an electrically insulating layer, which at least partially surrounds the nanoelement, as a charge storage layer and as a gate-insulating layer such that electrical charge carriers can be selectively introduced into or removed from the electrically insulating layer and an electrical conductivity of the nanoelement can be influenced in a characteristic way by electrical charge carriers introduced in the electrically insulating layer.