US Patent 8203179 - Complex oxide nanodot memory transistor

http://www.freepatentsonline.com/8203179.html

This patent from Micron Technology teaches using "nanodot" structures in a perovskite thin film for a charge trapping layer in order to scale memory transistors beyond the capability of SONOS or Flash non-volatile memory. Claim 1 reads:

1. A device having a memory cell, the memory cell comprising:

an active area formed of a semiconductor material;

a first dielectric over the semiconductor material;

a second dielectric comprising a material having a perovskite structure over the first dielectric, wherein the second dielectric comprises a plurality of spaced-apart nanodots, wherein the nanodots have a density in the range of about 1×10¹¹/cm² to about 1×10¹⁴/cm²;

a third dielectric over the second dielectric; and

a gate electrode over the third dielectric.                             

US Patent 8088643 - Memresistor with nanoparticle assisted filament formation

http://www.freepatentsonline.com/8088643.html

Since the late 1990's Micron Technology has been experimenting with new types of non-volatile memory based on ionic chalcogenide materials. This latest patent teaches how nanoparticles can be used to assist in filament electroformation of these memories. Claim 1 reads:
1. A method of forming a memory device, comprising:

providing a first electrode;

providing a nanoparticle over said first electrode;

providing a chalcogenide glass over and surrounding the nanoparticle except where the nanoparticle is in contact with said first electrode; and

providing a second electrode over said chalcogenide glass.

US Patent 8067803 - Nanoparticle recombination sites built into DRAM memory transistor

http://www.freepatentsonline.com/8067803.html

Conventional DRAM memory cells include both a capacitor and a transistor but there has been an effort to produce DRAM cells without capacitors to decrease the cell size. This patent from Micron teaches a variation of this approach using nanoparticles as recombination sites for capacitor-less charge storage. Claim 1 reads:

1. A memory device comprising:

a partially depleted storage transistor at a surface of a substrate comprising:

a body portion located between a first source/drain region and a second source/drain region, the body portion including a heavily doped region of a second conductivity type having one of nano-particles and nano-inclusions located therein adjacent to the second source/drain region and separated from the first source/drain region, the first source/drain region and the second source/drain region comprising:

regions of a first conductivity type, and a gate structure, the gate structure wrapping at least partially around a body portion in at least two spatial planes;

a bit line connected to the first source/drain region; and

a word line connected to the gate structure.

US Patent 8057686 - Molecular tag for nanotube separation

http://www.freepatentsonline.com/8057686.html

This patent from Micron Technology teaches a method of removing defective carbon nanotubes based on molecular tags which are chemisorbed on defective portions of the nanotubes.

1. A defective nanotube separation method comprising:

depositing by atomic layer deposition a tag on a nanotube having a conductive, semiconductive, or insulative type of intrinsic conductivity in a nanotube mixture, the nanotube having a defect, the tag depositing at the defect where a deposition rate is greater than on another nanotube in the mixture lacking the defect, the other nanotube having the same type of intrinsic conductivity as the tagged nanotube, and the tag not depositing on the other nanotube;

removing the tagged nanotube from the mixture by using the tag; and

after the removing, the mixture containing the untagged other nanotube having the same type of intrinsic conductivity as the tagged nanotube.

US Patent 8052075 - Microwave purification of single walled carbon nanotubes

http://www.freepatentsonline.com/8052075.html


This patent from Micron Technology teaches a way to remove the metallic type of single walled carbon nanotubes leaving single walled nanotubes useful as semiconducting material. Claim 1 reads:

1. A process, comprising:

treating a mixture of metallic carbon nanotubes and semiconductive carbon nanotubes in a liquid by applying microwave energy, the liquid selected such that the semiconductive carbon nanotubes do not significantly decompose in the liquid,

wherein treating the mixture is carried out under conditions of applying the microwave energy to the liquid containing the metallic carbon nanotubes and semiconductive carbon nanotubes to remove metallic carbon nanotubes but to leave semiconductive carbon nantoubes.

US Patent 8049514 - Nanotube electron emitter for IC inspection

http://www.freepatentsonline.com/8049514.html

This patent from Micron Technology teaches a way to improve the resolution of in situ monitoring during the fabrication of integrated circuits by using electron emitting carbon nanotubes in place or the more conventional optical probing methods. Claim 1 reads:

1. A system for testing integrated circuit substrates, comprising:

a nanotube emitter assembly to transmit an electrical signal to an integrated circuit substrate; and

a sensor electrically coupled to the nanotube emitter assembly to sense current associated with the electrical signal and induced through the integrated circuit substrate,

wherein the nanotube emitter assembly is configured to dry etch insulation material from an incompletely etched recess of the integrated circuit substrate.

US Patent 8034315 - Method of forming CNT electronics

http://www.freepatentsonline.com/8034315.html

This patent from Micron Technology teaches a way that carbon nanotube fibers can be arranged to form memory cells capable of storing multi-bit states. Claim 1 reads:

1. A method of forming a device, comprising:

providing a plurality of crossed carbon nanotubes over a semiconductor substrate, the crossed carbon nanotubes forming an undulating upper topography extending across the carbon nanotubes and within spaces between the carbon nanotubes, the spaces having maximum lateral widths, a global maximum lateral width being the greatest lateral width of any of the spaces; and

depositing a material over the crossed nanotubes, the material being deposited as particles that have minimum cross-sectional equatorial widths exceeding the global maximum lateral width.

US Patent 8030168 - Nanowhisker DRAM

http://www.freepatentsonline.com/8030168.html

This patent from Micron Technology proposes a method to increase the density of DRAM memory cells by growing semiconductor nanowhiskers to form capacitive structures. Claim 1 reads:

1. A method of forming a DRAM memory cell, comprising:

forming a wordline over a semiconductor substrate, and forming a capacitor storage node contact proximate the wordline;

growing a nanowhisker to have at least two dimensions of about 100 nanometers or less from beneath a catalytic material and from the capacitor storage node contact, and providing the nanowhisker to be electrically conductive; and

forming a capacitor dielectric layer and an outer capacitor electrode layer over the nanowhisker.

US Patent 8011296 - Supercritical fluid assisted printing of nanoparticles

http://www.freepatentsonline.com/8011296.html

This patent from Micron Technology discloses a high throughput deposition method for a pattern of nanoparticles using a maskless technique which does not require photolithography. Claim 1 reads:

1. A system for the maskless writing of a pattern on a substrate, comprising:

a support;

an unmasked substrate supported by the support;

a discharge assembly for masklessly discharging a solution directly to a surface of the unmasked substrate, the solution comprising nanometer-sized particles dissolved or dispersed in a supercritical fluid; and

a charging device for electrically charging the nanometer-sized particles.

US Patent 7927948 - Ion implantation nanocrystal growth

http://www.freepatentsonline.com/7927948.html

It has been proposed to use nanocrystals as a replacement for floating gates to improve the scalability of non-volatile memory transistors. However, during the manufacture of nanocrystal transistors too few nanocrystals can lead to difficulty in controlling the current in the transistor channel while too many nanocrystals results in current leakage which eliminates the ability to store charge. This patent from Micron Technology teaches a solution to optimize nanocrystal density which may improve scalability on non-volatile memory transistors into the nanoscale. Claim 1 reads:

1. A method of growing nanoscale structures on a semiconductor substrate, comprising:

implanting the semiconductor substrate with ions at a selected energy and a selected dose such that a controlled distribution of nucleation sites embedded in a surface of an insulative layer is formed, the surface disposed away from an interface formed by the insulative layer disposed on the semiconductor substrate, implanted material of the ions in the surface being the nucleation sites arranged to seed growth of nanoscale structures; and

growing conductive nanoscale structures from the nucleation sites on the insulative layer by depositing material on the nucleation sites of the implanted material in the surface.

US Patent 7883927 - Sorting nanotubes in plasma

http://www.freepatentsonline.com/7883927.html

This patent from Micron Technology teaches a new method of sorting carbon nanotubes by length to enable integration with semiconductor fabrication. Claim 1 reads:

1. A method, comprising:

providing a bundle of nanotubes;

suspending the nanotubes in a plasma to provide plasma-suspended nanotubes; and

sorting the plasma-suspended nanotubes according to size and separating the plasma-suspended nanotubes from remnant material using a motive force.

US Patent 7875912 - Atomic layer deposition of high-k dielectric

http://www.freepatentsonline.com/7875912.html

One route toward increased scaling of MOSFET electronics is the use of high-k materials to replace the silicon oxide used in current gate dielectrics. This patent from Micron teaches a new dielectric based on Zr(x)Hf(y)Sn(1-x-y)O2 material formed by atomic layer deposition. Claim 1 reads:

1. An electronic device comprising:

an amorphous dielectric layer containing at least one atomic layer deposited dielectric layer including zirconium oxide, hafnium oxide and tin oxide layers in an integrated circuit; and

a conductive layer contacting the dielectric layer.

US Patent 7859036 - Memristive memory with conical nanowire electrode

http://www.freepatentsonline.com/7859036.html

This patent from Micron Technology teaches another variation of memristive memory using conically shaped nanowires to reduce the energy required to write and erase memory states. Claim 1 reads:

1. A memory device comprising at least one memory cell having

an anode,

a cathode, and

a volume of variable resistance material disposed between the anode and the cathode,

at least one of the anode and the cathode comprising a single nanowire having one end thereof in electrical contact with the variable resistance material,

wherein the at least one of the anode and the cathode comprising the single nanowire further comprises a generally conical-shaped conductive catalytic structure comprising a catalyst material with the single nanowire formed on a tip thereof.

US Patent 7851292 - CNT floating gate memory

http://www.freepatentsonline.com/7851292.html

This patent from Micron Technologies teaches a way to form floating gate memory cells used in Flash memory with carbon nanotubes in the transistor channels to facilitate ballistic electron injection. Claim 1 reads:

1. A method of forming a floating-gate memory cell, comprising:

forming source/drain regions in a semiconductor substrate, wherein the source/drain regions define a channel region therebetween;

forming a plurality of carbon nanotubes overlying at least a portion of the channel region;

forming a tunnel dielectric layer overlying the carbon nanotubes;

forming a floating-gate layer overlying the tunnel dielectric layer;

forming an intergate dielectric layer overlying the floating-gate layer; and

forming a control gate layer overlying the intergate dielectric layer.

US Patent 7819005 - Resonant nanotube device

http://www.freepatentsonline.com/7819005.html

This patent from Micron Technology exploits the property of carbon nanotubes that mechanical deformation alters resistivity thus allowing for the creation of new nanotube sensors and transducers. Claim 1 reads: 

1. A sensor/transducer device, comprising:

at least one nanotube having a first end structurally and electrically coupled to a first electrode and a second end structurally and electrically coupled to a second electrode; and

at least one element configured to selectively adjust a resonant frequency of the at least one nanotube;

wherein the at least one element comprises at least one piezoelectric element.

US Patent 7799196 - Electromagnetic sorting and deposition of nanotubes

http://ip.com/patent/US7799196

This patent from Micron Technology teaches a carbon nanotube deposition method which includes a step of filtering and aligning the nanotubes by size. Claim 1 reads:

1. A method of depositing nanotubes onto a workpiece, comprising:

contacting a surface of a semiconductor wafer with a deposition fluid containing a plurality of nanotubes;

separating a first portion of the nanotubes from a second portion of the nanotubes with a filter located between the contacted surface of the semiconductor wafer and a counter-electrode;

aligning the first portion of the nanotubes relative to the surface of the semiconductor wafer while the first portion of the nanotubes are separated from the second portion of the nanotubes; and

establishing an energy field between the surface of the semiconductor wafer and the counter-electrode in the deposition fluid to deposit the separated and aligned first portion of the nanotubes onto the semiconductor wafer, wherein the energy field is at least one of an electric field and an electromagnetic field.

US Patent 7795725 - Carbon nanostructure mat for thermal cooling

http://ip.com/patent/US7795725

There has been much academic and some industry interest in the use of carbon nanostructures to form channels for future transistors. However, more near term applications in electronics may depend on the thermal cooling advantages offered by carbon nanostructures to semiconductor packaging. This latest patent from Micron Technology follows other companies including Intel and Hon Hai Precision in teaching a way to use carbon nanotubes to cool semiconductor dies. Claim 1 reads: 

1. A semiconductor package, comprising:

a semiconductor die;

a thermally conductive material in thermal contact with the die and comprising carbon nanostructures; and

wherein the semiconductor die has a substantially planar backside surface; and

wherein the thermally conductive material is a mat of the carbon nanostructures extending across an entirety of said substantially planar backside surface.

US Patent 7728626 - Nanolaminate transistor logic array

http://www.freepatentsonline.com/7728626.html

This patent from Micron teaches a transistor architecture using nanolaminate charge trapping structures for higher density programmable logic. Claim 1 reads:

1. A programmable logic array, comprising:

a plurality of input lines for receiving an input signal;

a plurality of output lines; and

one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal,

wherein each logic cell includes a transistor cell including:

a first source/drain region;

a second source/drain region;

a channel region between the first and the second source/drain regions, and

a gate separated from the channel region by a gate insulator; and

wherein the gate insulator includes oxide insulator nanolaminate layers wherein at least one charge trapping layer in the oxide insulator nanolaminate layers is substantially amorphous.

US Patent 7727786 - Photonic DRAM with nanotube layer

http://www.freepatentsonline.com/7727786.html

DRAM is popular as the main memory in personal computers due to its simplicity and small size. However, the requirement for frequent memory refreshing makes DRAM highly inefficient. This patent from Micron teaches a photonic memory variation in which the bits are stored based on photons in a phosphorescent material and in which aligned nanotube arrays are used to reduce crosstalk between adjacent memory cells. Claim 1 reads:

1. A method of fabricating a memory die, comprising the steps of:

forming a semiconductor substrate supporting a memory cell array, the memory cell array formed by:

forming a plurality of pixels on the semiconductor substrate, each pixel capable of emitting and receiving light; and

forming a material over the plurality of pixels, the material having nanotubes formed therein, the nanotubes having phosphorescent material localized over each pixel, the phosphorescent material capable of receiving light from and emitting light to the pixel; and

electrically coupling the memory cell array to the semiconductor substrate.

US Patent 7687841 - Offset gate CNTFET

http://www.freepatentsonline.com/7687841.html

This patent from Micron Technologies addresses the problem of leakage current between the drain and source of carbon nanotube field effect transistors by placing the gate electrode at an asymmetric position. Claim 1 reads:

1. A transistor, comprising:

a channel formed of at least one carbon nanotube, wherein the channel is in contact with a source and with a drain of the transistor;

a dielectric material proximate to the channel; and

a gate comprising a sidewall on an edge of a pad, wherein the gate is proximate to the dielectric material, wherein the gate is positioned closer to the source than to the drain, and wherein the source and drain are self aligned with respect to the gate and to the pad.