US Patent 7667260 - Nanorod floating gate memory cell
In order to continue the scaling of flash memory there has been an increase in patents which incorporate nanostructures in memory cell design. This latest patent from Micron teaches a structure which reduced parasitic capacitance effects using a nanorod floating gate. Claim 1 reads:
1. A memory cell, comprising:
a tunnel dielectric layer overlying a semiconductor substrate;
a floating gate having a conductive first layer overlying the tunnel dielectric layer and a conductive nanorod having a longest dimension extending from the conductive first layer in an approximately perpendicular direction relative to the surface of the tunnel dielectric layer; and
a control gate layer separated from the floating gate by an intergate dielectric layer.
Labels: Micron Technology