US Patent 7484423 - Integrated circuit quality analysis using carbon nanotube FET
http://www.freepatentsonline.com/7484423.html
The fabrication techniques necessary to produce a high density of carbon nanotube transistors on a substrate do not currently exist but this patent from IBM teaches that CNT transistors can other uses in quality analysis which may be more easily implemented in the near term. Claim 1 reads:
1. A method of evaluating operating parameters of an integrated circuit, said method comprising:
providing a primary transistor in said integrated circuit;
embedding a carbon nanotube field effect transistor (CNT FET) in said integrated circuit, wherein a nanotube portion of said CNT FET is separate from said primary transistor;
operating said primary transistor;
detecting signals from said CNT FET corresponding to said operating parameters of said primary transistor in said integrated circuit; and
detecting defective circuits within said integrated circuit by measuring stress and strain of said primary transistor in said integrated circuit using said CNT FET, wherein said stress and strain comprise any of mechanical and thermal stress and strain.
The fabrication techniques necessary to produce a high density of carbon nanotube transistors on a substrate do not currently exist but this patent from IBM teaches that CNT transistors can other uses in quality analysis which may be more easily implemented in the near term. Claim 1 reads:
1. A method of evaluating operating parameters of an integrated circuit, said method comprising:
providing a primary transistor in said integrated circuit;
embedding a carbon nanotube field effect transistor (CNT FET) in said integrated circuit, wherein a nanotube portion of said CNT FET is separate from said primary transistor;
operating said primary transistor;
detecting signals from said CNT FET corresponding to said operating parameters of said primary transistor in said integrated circuit; and
detecting defective circuits within said integrated circuit by measuring stress and strain of said primary transistor in said integrated circuit using said CNT FET, wherein said stress and strain comprise any of mechanical and thermal stress and strain.
Labels: IBM
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