US Patent 8183554 - Memresistor crossbar structure with built-in rectification
http://www.freepatentsonline.com/8183554.html
ReRAM is a new type of non-volatile memory architecture which is predicted to begin replacing Flash, DRAM, and SRAM as a "universal memory" by 2013. One of the problems with ReRAM memory arrays is the existence of sneak paths which limit the size and density of the memory cells. There are some approaches using diodes and other non-linear elements to avoid sneak paths but these solutions result in asymmetrical write/erase voltages. This is one of my patents teaching crossbar architectures which avoid sneak paths while providing symmetry in write and erase voltages. Claim 5 reads:
5. A crossbar structure comprising:
a first layer or layers including a first array of p-type input wires and a first array of n-type output wires;
a second layer or layers including a second array of p-type input wires and a second array of n-type output wires; and
a resistance programmable material formed between the first layer(s) and the second layer(s),
wherein the first array of p-type input wires are not parallel with the second array of n-type output wires and the second array of p-type input wires are not parallel with the first array of n-type output wires.
ReRAM is a new type of non-volatile memory architecture which is predicted to begin replacing Flash, DRAM, and SRAM as a "universal memory" by 2013. One of the problems with ReRAM memory arrays is the existence of sneak paths which limit the size and density of the memory cells. There are some approaches using diodes and other non-linear elements to avoid sneak paths but these solutions result in asymmetrical write/erase voltages. This is one of my patents teaching crossbar architectures which avoid sneak paths while providing symmetry in write and erase voltages. Claim 5 reads:
5. A crossbar structure comprising:
a first layer or layers including a first array of p-type input wires and a first array of n-type output wires;
a second layer or layers including a second array of p-type input wires and a second array of n-type output wires; and
a resistance programmable material formed between the first layer(s) and the second layer(s),
wherein the first array of p-type input wires are not parallel with the second array of n-type output wires and the second array of p-type input wires are not parallel with the first array of n-type output wires.
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