US Patent 8154010 - PN nanotube network crossbar memory
http://www.freepatentsonline.com/8154010.html
This patent from Hynix Semiconductor teaches how to form a memory array using p-doped and n-doped nanotube networks as a future replacement for DRAM. Claim 1 reads:
1. A memory device having a crossbar structure, the memory device comprising:
a plurality of first electrodes arranged in parallel and extending in a first direction;
a plurality of second electrodes arranged in parallel, spaced apart from the first electrodes, and extending in a second direction intersecting the first direction; and
a first nanotube or nanowire network disposed at each intersection of the first electrodes and the second electrodes, including a stacked structure of a P-type network and an N-type network, and having a diode characteristic, the stacked structure comprising an upper portion, a lower portion, and a heterojunction defined between the upper portion and the lower portion, one of the upper or lower portions being the P-type network, and the other one of the upper or the lower portions being the N-type network, wherein each of the first electrodes is connected to one of the P-type network and the N-type network and each of the second electrodes is connected to the other of the P-type network and the N-type network.
This patent from Hynix Semiconductor teaches how to form a memory array using p-doped and n-doped nanotube networks as a future replacement for DRAM. Claim 1 reads:
1. A memory device having a crossbar structure, the memory device comprising:
a plurality of first electrodes arranged in parallel and extending in a first direction;
a plurality of second electrodes arranged in parallel, spaced apart from the first electrodes, and extending in a second direction intersecting the first direction; and
a first nanotube or nanowire network disposed at each intersection of the first electrodes and the second electrodes, including a stacked structure of a P-type network and an N-type network, and having a diode characteristic, the stacked structure comprising an upper portion, a lower portion, and a heterojunction defined between the upper portion and the lower portion, one of the upper or lower portions being the P-type network, and the other one of the upper or the lower portions being the N-type network, wherein each of the first electrodes is connected to one of the P-type network and the N-type network and each of the second electrodes is connected to the other of the P-type network and the N-type network.
Labels: Hynix Semiconductor
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