US Patent 7880163 - Surrounding gate nanowire JFET
http://www.freepatentsonline.com/7880163.html
MOSFETs are the most common type of transistor used for digital electronics and include different doping types for the channel and the source/drain regions (n-type vs. p-type). However, when the channel is formed with a nanowire the surface roughness of the nanowire can be detrimental to the mobility of the MOSFET. This patent from IMEC teaches a different type of junction transistor based on a uniformly doped nanowire. Claim 1 reads:
1. A nanostructure-insulated junction field effect transistor comprising:
a uniformly doped nanostructure having a length LN and a radius R, wherein the uniformly doped nanostructure has a dopant concentration profile that is uniform along the central symmetry axis and the longitudinal axis;
a gate electrode wrapped at least partially around the uniformly doped nanostructure and having a length LG; and
an insulating layer having a thickness tox wrapped at least partially around the uniformly doped nanostructure and situated in between the uniformly doped nanostructure and the gate electrode,
wherein the insulating layer covers the uniformly doped nanostructure along its longitudinal axis such that the gate electrode makes no direct contact with the uniformly doped nanostructure.
MOSFETs are the most common type of transistor used for digital electronics and include different doping types for the channel and the source/drain regions (n-type vs. p-type). However, when the channel is formed with a nanowire the surface roughness of the nanowire can be detrimental to the mobility of the MOSFET. This patent from IMEC teaches a different type of junction transistor based on a uniformly doped nanowire. Claim 1 reads:
1. A nanostructure-insulated junction field effect transistor comprising:
a uniformly doped nanostructure having a length LN and a radius R, wherein the uniformly doped nanostructure has a dopant concentration profile that is uniform along the central symmetry axis and the longitudinal axis;
a gate electrode wrapped at least partially around the uniformly doped nanostructure and having a length LG; and
an insulating layer having a thickness tox wrapped at least partially around the uniformly doped nanostructure and situated in between the uniformly doped nanostructure and the gate electrode,
wherein the insulating layer covers the uniformly doped nanostructure along its longitudinal axis such that the gate electrode makes no direct contact with the uniformly doped nanostructure.
Labels: IMEC
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