US Patent 7732859 - CMOS compatible graphene FET
http://www.freepatentsonline.com/7732859.html
Although the discovery of carbon nanotubes is often credited to Sumio Iijima of NEC, the first examples of single walled carbon nanotubes and nanotube transistors were developed by researchers from IBM. This patent from IBM continues their tradition in advancing the state of the art in carbon-based electronics by teaching how to manufacture field effect transistors based on graphene. Claim 1 reads:
1. A field effect transistor comprising:
a silicon carbide fin located directly on a silicon carbide substrate;
a pair of graphene layers located on a pair of sidewalls of said silicon carbide fin;
doped source and drain regions located between said pair of graphene layers and within said silicon carbide fin, said doped source and drain regions comprising a doped silicon carbide material;
a channel comprising a channel portion of said pair of graphene layers and contacting said doped source and drain regions; a gate dielectric directly contacting said channel portion within said pair of graphene layers; and
a gate electrode directly contacting said gate dielectric.
Although the discovery of carbon nanotubes is often credited to Sumio Iijima of NEC, the first examples of single walled carbon nanotubes and nanotube transistors were developed by researchers from IBM. This patent from IBM continues their tradition in advancing the state of the art in carbon-based electronics by teaching how to manufacture field effect transistors based on graphene. Claim 1 reads:
1. A field effect transistor comprising:
a silicon carbide fin located directly on a silicon carbide substrate;
a pair of graphene layers located on a pair of sidewalls of said silicon carbide fin;
doped source and drain regions located between said pair of graphene layers and within said silicon carbide fin, said doped source and drain regions comprising a doped silicon carbide material;
a channel comprising a channel portion of said pair of graphene layers and contacting said doped source and drain regions; a gate dielectric directly contacting said channel portion within said pair of graphene layers; and
a gate electrode directly contacting said gate dielectric.
Labels: IBM
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