Thursday, March 04, 2010

US Patent 7671612 - Integrated compound nanoprobe card

The electrical testing of semiconductor wafers often involves probe cards which are used to establish an electrical path between a test circuit and the semiconductor. In the past the test pins of the probe cards have been limited to a pitch > 50 microns when using conventional manufacturing techniques. This patent from Industrial Technology Research Institute teaches using arrays of nanotubes or nanorods to increase the resolution of the pins. Claim 1 reads:

1. A probe pin set comprising:

a substrate having a porous surface; and

a plurality of pins arranged in said porous surface of said substrate subject to a predetermined pattern and extended in direction substantially perpendicular to said porous surface of said substrate,

said pins each having a bundle of aligned parallel nanotubes/nanorods and a bonding material bonded to said bundle of aligned parallel nanotubes/nanorods and filled in gaps in said nanotubes/nanorods, wherein said bonding material consists essentially of a metal material.