Sunday, October 12, 2008

US Patent 7433237 - Transistor utilizing dielectric oxide nanolaminates

This patent from Micron Technology teaches a transistor structure for DRAM memory cells that uses oxide nanolaminate dielectrics for enhanced read/write speeds with reduced cell sizes. Claim 1 reads:

1. A transistor device, comprising:

a first source/drain region;

a second source/drain region;

a channel region between the first and the second source/drain regions; and

a gate separated from the channel region by a multilayer gate insulator; wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; and

circuitry coupled to the source/drain regions to program the transistor in a first direction, and read the transistor in a second direction opposite the first direction.