Wednesday, June 13, 2007

US Patent 7230286 - Silicided bottom contact for nanowire FET

In vertical FETs the current flows through a vertical channel extending from a substrate in a direction perpendicular to the plane of the substrate. However, when nanowires are used for the vertical channels the contact resistance can be too high. This patent from IBM teaches using a silicide (i.e. metal-silicon compound) to reduce the contact resistance. Claim 1 reads:

1. A semiconductor structure comprising: a silicide contact layer located within, or on a portion of a semiconductor substrate; a plurality of nanowires located on said silicide contact layer; a gate dielectric surrounding said plurality of nanowires; a gate conductor located on said gate dielectric; and a source and drain located at each end of said nanowires.

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