Thursday, June 07, 2007

US Patents 7227379 and 7228518 - Nanowire crossbar arrays

Of all of the different approaches to nanoelectronic architectures I've come across the approach taken by Hewlett Packard (nanowire crossbar arrays) seems the most likely to have a substantial impact in the next 5-10 years. Some of the advantages of HPs approach are as follows:

1) Many of the proposed implementations of nanowire crossbars complement rather than attempt to replace more conventional electronics. Hybrid systems based on HP's nanowire crossbars such as CMOL (combining CMOS and molecular electronics) are in the works. This can facilitate a less disruptive, and thus more easily acceptable, electronics platform on which molecular based electronics may flourish.

2) The manufacturing of these devices are fairly cost effective since they are based on regular, periodic structures and complex patterning is not necessary. HP has advanced technologies such as nanoimprint lithography which provide for cheaper avenues of fabrication than the traditional EUV lithography and the capability of process scaling for mass production. HP is also supporting or working with other smaller companies to promote the use of nanoimprint lithography.

3) HP is creating a learning base based on applications in high-density resistive memory which may be applied to niche applications controlled by HP such as the non-volatile memorys used in inkjet print cartridges. The lessons learned in nanowire crossbar memory devices will undoubtably pay off as applications in nanowire crossbar processors come into fruition.

4) The nanowire crossbar architectures presents new capabilities beyond what is offered by silicon by providing the ability to form electronics on flexible (e.g. plastic) substrates and by allowing for reconfigurability (allowing for circuit self-repair and ease of integration with adaptive electronic systems such as FPGAs).

These are two of the most recent patents and representative claims from HP on this technology-one dealing with the creation of 1 bit register arrays and the other on how multilevel nanowire crossbar arrays may be formed by folding the substrate on which the nanowires are placed.

1. A nanoscale computing engine comprising: a nanowire data bus; a plurality of nanoscale registers interconnected by the nanowire data bus, each nanoscale register driven by a nanoscale control line; and primitive operations, each primitive operation composed of one or more inputs to one or more of the nanowire data bus and nanoscale control lines, that provide for transfer of information from an external source to a specified nanoscale register, transfer of information from a nanoscale register source to an external target, and transfer of information from a first nanoscale register to a second nanoscale register.

1. A method for obtaining a multilayer nanowire-crossbar design that is functionally equivalent to a two-layer nanowire crossbars design, the method comprising: receiving the two-layer nanowire-crossbar design having two or more microregions; folding the two-layer nanowire-crossbar design between the two or more microregions; and collapsing folded nanowires into single nanowires, which yields the multilayer nanowire-crossbar design.

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