Monday, April 04, 2011

US Patent 7916530 - Mem-resistor storage matrix

This patent from Contour Semiconductor has priority going back to 2003 and appears to include some claims relevant to arrays of memory resistors which are being planned for nanoscale non-volatile memory by several different companies (HP, Sharp, Micron). This particular patent appears to teach similar subject matter from that of Unity Semiconductor patents which have slightly earlier priority but were not considered during examination (e.g. US Patent 6870755). For more details on the business developments surrounding memory resistance electronics see this link.

Claim 1 reads:

1. An addressable storage matrix facilitating control over excessive current leakage, the matrix comprising:

a first plurality of intersection points at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the threshold is exceeded,

each non-linear element exhibiting, at a given voltage and independent of the bit state for its corresponding intersection point, a first current level or a second current level greater than the first current level,

the non-linear element exhibiting the second current level at the given voltage only if the non-linear element has been subjected to a voltage at least equal to the threshold; and

disposed at each intersection point bridged by a two-terminal non-linear element, a programmable material in series with the two-terminal non-linear element and determining a bit state for the corresponding intersection point.