US Patent 7727830 - Ge nanowire FinFET
http://www.freepatentsonline.com/7727830.html
Germanium was an early contender as the material used to form transistors due to a high mobility. Eventually silicon won out despite having a lower mobility due to the ease of forming SiO2 dielectric on the silicon surface. This patent from Intel proposes a transistor design going back to germanium and provides a FinFET structure allowing for further scaling to nanometer dimensions. Claim 1 reads:
1. A method comprising:
forming an silicon fin surrounded by trench isolation regions in a semiconductor substrate;
forming a silicon germanium layer over the silicon fin;
forming oxide masking layers at two end regions of the silicon fins;
exposing the silicon germanium layer in middle region of the silicon fin to preferential silicon oxidation to form a germanium nanowire in the middle region of the silicon fin and silicon germanium pillar anchors at the two oxide masked end regions of the silicon fin;
forming an dielectric layer over the substrate; forming a conducting layer over the dielectric layer; and
forming a polysilicon gate line.
Germanium was an early contender as the material used to form transistors due to a high mobility. Eventually silicon won out despite having a lower mobility due to the ease of forming SiO2 dielectric on the silicon surface. This patent from Intel proposes a transistor design going back to germanium and provides a FinFET structure allowing for further scaling to nanometer dimensions. Claim 1 reads:
1. A method comprising:
forming an silicon fin surrounded by trench isolation regions in a semiconductor substrate;
forming a silicon germanium layer over the silicon fin;
forming oxide masking layers at two end regions of the silicon fins;
exposing the silicon germanium layer in middle region of the silicon fin to preferential silicon oxidation to form a germanium nanowire in the middle region of the silicon fin and silicon germanium pillar anchors at the two oxide masked end regions of the silicon fin;
forming an dielectric layer over the substrate; forming a conducting layer over the dielectric layer; and
forming a polysilicon gate line.
Labels: Intel
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