Friday, December 14, 2007

US Patent 7307448 - Interconnectable nanoscale computational stages

Hewlett-Packard has been developing nanowire crossbar architectures over the past several years for applications in high density and memory devices. This patent focuses on the interconnection of nanoscale logic and memory devices to construct computational devices. Claim 1 reads:

1. A nanoscale computational stage comprising: a nanoscale logic array formed by interconnections between a number of internal signal lines, a number of logic-array input lines, and a number of logic-array output lines; and a number of nanoscale latch arrays interconnected with the nanoscale logic array, wherein each nanoscale latch array includes at least one enable line, a first control line, and a second control line that are selectively interconnected with the logic-array output lines and/or the logic-array input lines.