Thursday, March 15, 2007

US Patent 7189635 - Interlaced nanowire fabrication

The fabrication of nanowires on a substrate often employs non-conventional manufacturing processes such as self-assembly and nanoimprint lithography. This patent from HP proposes a mixture of processes, the first of which forms a first array of parallel nanowires and the second of which reduces the diameters of the first nanowires to form a second set of nanowires between the first nanowires so as to allow for higher wire densities to be formed. Claim 1 reads:

1. A method of reducing feature dimensions of a nano-scale device comprising: consuming a surface of a device substrate, the device having a pattern of spaced apart first nanowires on the surface, the consumption reducing a dimension of the first nanowires; and forming a second nanowire in a trench between adjacent ones of the first nanowires, such that the device comprises a set of features that includes the first nanowires with the reduced dimension and the second nanowire spaced from the adjacent first nanowires by sub-trenches.

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