US Patent 8065634 - Analysis of nanotube logic circuits
http://www.freepatentsonline.com/8065634.html
This patent from Stanford University teaches designing and forming nanotube logic circuits that are immune to misaligned or misplaced carbon nanotubes. Claim 1 reads:
1. A method for validating that a nanotube logic network having a plurality of regions is immune to misaligned nanotubes, the method comprising:
determining, by a computing device comprising a processor, each separate path through a plurality of adjoining regions of the plurality of regions from an input contact region to an output contact region, wherein each of the plurality of regions has an assigned Boolean function based on a conductivity of the respective region, wherein the plurality of regions comprises at least one gate region and at least one nonconductive region or doped region;
determining, by the computing device, a path function for each separate path based on the assigned Boolean function of each of the plurality of adjoining regions in the separate path;
determining, by the computing device, a combined path function based on the path function for each separate path; and
validating the nanotube logic network if the combined path function is equivalent to an intended logic function of the nanotube logic network.
This patent from Stanford University teaches designing and forming nanotube logic circuits that are immune to misaligned or misplaced carbon nanotubes. Claim 1 reads:
1. A method for validating that a nanotube logic network having a plurality of regions is immune to misaligned nanotubes, the method comprising:
determining, by a computing device comprising a processor, each separate path through a plurality of adjoining regions of the plurality of regions from an input contact region to an output contact region, wherein each of the plurality of regions has an assigned Boolean function based on a conductivity of the respective region, wherein the plurality of regions comprises at least one gate region and at least one nonconductive region or doped region;
determining, by the computing device, a path function for each separate path based on the assigned Boolean function of each of the plurality of adjoining regions in the separate path;
determining, by the computing device, a combined path function based on the path function for each separate path; and
validating the nanotube logic network if the combined path function is equivalent to an intended logic function of the nanotube logic network.
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