Sunday, April 11, 2010

US Patent 7692215 - Microscale to nanoscale electronic interface

HPLabs has attracted much attention recently based on the development of a new nanoscale circuit element called a memristor having potential applications in non-volatile memory and programmable logic. However, perhaps an equally important development from HPLabs is the development of nanoscale interfaces allowing further scaling than conventional semiconductor manufacturing would allow. This patent covers one approach using separate microscale and nanoscale layers. Claim 1 reads:

1. A nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer, the nanoscale/microscale interface comprising:

a microscale-layer substrate;

microelectronic circuits fabricated on the microscale-layer substrate, the microelectronic circuits connected to a number of pins exposed on a surface microscale-layer, the pins partitioned into groups of pins, each group of pins configured identically within a fundamental unit, the fundamental units arranged to tile the surface microscale-layer according to a lattice symmetry; and

a number of nanoscale-layer sub-layers, each nanoscale-layer sub-layer containing regularly spaced, parallel pad-interconnected-nanowire-unit (PINU) bundles.