Thursday, July 30, 2009

US Patent 7566657 - Nanoparticle based growth of interconnect vias

The development of 3D stacked semiconductor circuit architectures is of interest to continue Moore's Law. One issue in this area is the development of high aspect ratio vertical interconnects to connect the different layers. This patent from HP teaches using nanoparticle catalysts to induce the growth of such interconnects. Claim 1 reads:

1. A method of forming at least one through-substrate interconnect, comprising:

providing a semiconductor substrate having a first surface and an opposing second surface;

forming at least one opening in the semiconductor substrate, the at least one opening extending from the first surface to an intermediate depth within the semiconductor substrate, the at least one opening partially defined by a base;

providing at least one metal-catalyst nanoparticle on the base instead of the sidewalls;

growing conductive material within the at least one opening under conditions in which the metal-catalyst nanoparticle promotes deposition of the conductive material onto the base; and

removing material of the semiconductor substrate from the second surface to expose a portion of the conductive material filling the at least one opening.