US Patent 7242601- Microscale to nanoscale memory addressing
http://www.freepatentsonline.com/7242601.html
A variety of memory and logic systems are currently being developed by companies such as Hewlett packard and Nantero using nanoscale crossbars. One difficulty in working with nanoscale crossbars is addressing the nanowires using microscale wires. Andre DeHon is an inventor at CalTech working on realizing a variety of solutions to this problem. This solution uses a particular coding system for microscale to nanoscale wiring interfaces. Claim 1 reads:
1. A method for addressing a memory comprising: selecting a nanoscale wire from a plurality of nanoscale wires through a first set of microscale inputs; associating a code to the selected nanoscale wire through a second set of microscale inputs; repeating the selecting and associating steps in accordance with a number of nanoscale wires to be programmed; associating memory addresses of the memory to codes associated with the selected nanoscale wires; and selecting memory addresses of the memory by means of the second set of microscale inputs.
A variety of memory and logic systems are currently being developed by companies such as Hewlett packard and Nantero using nanoscale crossbars. One difficulty in working with nanoscale crossbars is addressing the nanowires using microscale wires. Andre DeHon is an inventor at CalTech working on realizing a variety of solutions to this problem. This solution uses a particular coding system for microscale to nanoscale wiring interfaces. Claim 1 reads:
1. A method for addressing a memory comprising: selecting a nanoscale wire from a plurality of nanoscale wires through a first set of microscale inputs; associating a code to the selected nanoscale wire through a second set of microscale inputs; repeating the selecting and associating steps in accordance with a number of nanoscale wires to be programmed; associating memory addresses of the memory to codes associated with the selected nanoscale wires; and selecting memory addresses of the memory by means of the second set of microscale inputs.
Labels: Caltech, nanowire crossbar
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