US Patent 8212237 - Surrounding gate nanowire flash memory

http://www.freepatentsonline.com/8212237.html

This patent from QuNano teaches a charge trap based memory which help reduce the footprint of flash memory cells while allowing vertical stacking for 3D memory. Claim 1 reads:

1. A nanostructured memory device comprising:

at least one semiconductor nanowire forming a current transport channel;

one or more shell layers arranged around at least a portion of the nanowire;

nano-sized charge trapping centres embedded in said one or more shell layers, wherein a change in an amount of charge stored in one or more of the charge trapping centres alters the conductivity of the nanowire; and

at least a first gate electrode arranged around at least a portion of said one or more shell layers in order to control the amount of charge stored in the charge trapping centres under the gate electrode;

wherein said one or more shell layers are made of materials having different band gap in order to give a graded or crested band profile.