US Patent 7821061 - Ge/SiGe multigate nanowire transistor
http://www.freepatentsonline.com/7821061.html
In the early days of transistors germanium was considered as a leading semiconductor material since it has a superior high electron mobility which allows for fast switching. Silicon eventually became dominant due to better thermal stability and the ease of oxide growth on Si surfaces but as device miniaturization continues the relative benefits of Ge are being reconsidered. This patent from Intel proposes a transistor design based on both Si and Ge materials forming a nanowire channel. Claim 1 reads:
1. A microelectronic structure comprising:
a substrate including a lower Si substrate and an insulating layer on the substrate;
a projection on the substrate projecting above the insulating layer and including a center region comprising a floating nanowire channel comprising Ge/Si1-yGey and a covering region enclosing the center region, wherein the covering region comprises an insulation covering surrounding the nanowire channel and electrically insulating the nanowire channel and
wherein both the center region and an interface between the center region and the covering region has substantially no dislocation defects.
In the early days of transistors germanium was considered as a leading semiconductor material since it has a superior high electron mobility which allows for fast switching. Silicon eventually became dominant due to better thermal stability and the ease of oxide growth on Si surfaces but as device miniaturization continues the relative benefits of Ge are being reconsidered. This patent from Intel proposes a transistor design based on both Si and Ge materials forming a nanowire channel. Claim 1 reads:
1. A microelectronic structure comprising:
a substrate including a lower Si substrate and an insulating layer on the substrate;
a projection on the substrate projecting above the insulating layer and including a center region comprising a floating nanowire channel comprising Ge/Si1-yGey and a covering region enclosing the center region, wherein the covering region comprises an insulation covering surrounding the nanowire channel and electrically insulating the nanowire channel and
wherein both the center region and an interface between the center region and the covering region has substantially no dislocation defects.
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