US Patent 7525833 - Nanowire shift register
http://www.freepatentsonline.com/7525833.html
HP Labs has gradually been developing nanowire crossbar electronics over the past ten years offering a nanoscale alternative to purely the CMOS based architectures which dominate electronic design. This latest patent teaches using this type of architecture to construct a shift register. Claim 1 reads:
1. A nanoscale shift register comprising:
a first set of nanowires interconnected through a first set of latches to a first latch-control signal line; and
a second set of nanowires interconnected through a second set of latches to a second latch-control signal line, the nanowires of the first set of nanowires and the nanowires of the second set of nanowires arranged in a sequence that includes a first nanowire, a last nanowire, and a subsequence of internal nanowires between the first nanowire and the last nanowire, each internal nanowire of the second set of nanowires interconnected through a gate of a first set of gates controlled by a first gate signal line to a preceding nanowire of the first set of nanowires and interconnected through a gate of a second set of gates controlled by a second gate signal line to a next nanowire of the first set of nanowires.
HP Labs has gradually been developing nanowire crossbar electronics over the past ten years offering a nanoscale alternative to purely the CMOS based architectures which dominate electronic design. This latest patent teaches using this type of architecture to construct a shift register. Claim 1 reads:
1. A nanoscale shift register comprising:
a first set of nanowires interconnected through a first set of latches to a first latch-control signal line; and
a second set of nanowires interconnected through a second set of latches to a second latch-control signal line, the nanowires of the first set of nanowires and the nanowires of the second set of nanowires arranged in a sequence that includes a first nanowire, a last nanowire, and a subsequence of internal nanowires between the first nanowire and the last nanowire, each internal nanowire of the second set of nanowires interconnected through a gate of a first set of gates controlled by a first gate signal line to a preceding nanowire of the first set of nanowires and interconnected through a gate of a second set of gates controlled by a second gate signal line to a next nanowire of the first set of nanowires.
Labels: Hewlett Packard
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