Wednesday, April 01, 2009

US Patent 7510982 - Porous low-k films formed using sacrificial nanoparticles

The speed bottleneck in integrated circuit design usually comes from the interconnect lines which can generate capacitance that increases signal delays. To solve this problem there is an interest in low-k dielectrics which can be formed from porous oxides or polymers. This patent from Novellus Systems teaches a method using nanoparticles as pore forming structures for an integrated circuit dielectric layer. Claim 1 reads:

1. A method of fabricating an integrated circuit comprising:

embedding nanoparticles in a dielectric network on a substrate in a chamber to form a layer of composite dielectric material, wherein the nanoparticles are selected from silicon or carbon allotropes;

patterning the layer of composite dielectric material to define paths for the conductive lines and filling the paths with conductive material;

removing excess conductive material to thereby form an exposed pattern of conductive lines in the composite dielectric material; and removing at least some of the nanoparticles by UV-initiated photo-dissociation, thereby creating a porous dielectric network.