US Patent 7425487 - Nanoelement FET fabrication
http://www.freepatentsonline.com/7425487.html
Due to the expected difficulty in extending nanofabrication to sub-22 nm dimensions there is an increased interest from companies such as Infineon and Samsung in forming nanowires or nanotubes as channel elements for post-2012 FETs. This latest patent is from Qimonda a spin-off from Infineon focused on DRAM technology. Claim 1 reads:
1. A method for fabricating a nanoelement field effect transistor, the method comprising:
applying a nanoelement to a substrate;
forming a first source/drain region on and/or in the substrate, the first source/drain region being coupled to a first end portion of the nanoelement;
forming a second source/drain region on and/or in the substrate, the second source/drain region being coupled to a second end portion of the nanoelement;
removing a surface region of the substrate in such a manner that a region of the nanoelement arranged between the first and second end portions is uncovered over the entire periphery of the nanoelement;
forming a gate-insulating structure so as to cover the whole of the uncovered periphery of the nanoelement; and
forming a gate structure so as to cover the entire periphery of the gate-insulating structure.
Due to the expected difficulty in extending nanofabrication to sub-22 nm dimensions there is an increased interest from companies such as Infineon and Samsung in forming nanowires or nanotubes as channel elements for post-2012 FETs. This latest patent is from Qimonda a spin-off from Infineon focused on DRAM technology. Claim 1 reads:
1. A method for fabricating a nanoelement field effect transistor, the method comprising:
applying a nanoelement to a substrate;
forming a first source/drain region on and/or in the substrate, the first source/drain region being coupled to a first end portion of the nanoelement;
forming a second source/drain region on and/or in the substrate, the second source/drain region being coupled to a second end portion of the nanoelement;
removing a surface region of the substrate in such a manner that a region of the nanoelement arranged between the first and second end portions is uncovered over the entire periphery of the nanoelement;
forming a gate-insulating structure so as to cover the whole of the uncovered periphery of the nanoelement; and
forming a gate structure so as to cover the entire periphery of the gate-insulating structure.
Labels: Qimonda
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