Saturday, May 27, 2006

US Patent 7049625 - Nanowire FET With Defect

Basic memory elements often employ the trapping of electrical charge beneath a thin film insulating barrier of a field effect transistor. The inventors of this patent employ the same concept but use a defect region of a nanowire instead of a thin film insulator to store the charge.

Claim 1 reads:

1. Field effect transistor memory cell having a source region, a drain region, a channel region and a gate region, with the channel region extending from the source region to the drain region and being formed by at least one nanowire which has at least one defect such that charges can be trapped in and released from the defects by a voltage applied to the gate region.

Recently the USPTO published a classification outline for nanotechnology patents and one of the subclasses in this class is specifically devoted to FETs with nanowire gates (search ccl/977/938 at Currently there are 23 US patents listed in this field.